1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to the formation of ultra thin sidewall spacers adjacent the gate dielectric and gate conductor of a transistor.
2. Description of the Related Art
As shown in FIG. 1, a typical field effect transistor 10 is comprised of a gate dielectric 12 positioned above a surface 11 of a semiconducting substrate 13, a gate conductor 14 positioned above the gate dielectric 12, and a plurality of sidewall spacers 20 formed adjacent the gate dielectric 12 and gate conductor 14. The sidewall spacers 20 may be comprised of a variety of materials, such as, for example, silicon dioxide. Additionally, a typical transistor 10 is also comprised of a plurality of source/drain regions 16 formed in the substrate 13. Each of the source/drain regions 16 may also have extensions 18 which have a width corresponding to the dimension "X" shown in FIG. 1.
The transistor 10 depicted in FIG. 1 may be formed by a variety of known techniques. For example, the gate dielectric 12 and gate conductor 14 may be constructed by forming a plurality of process layers above the surface 11 of the substrate 13 and, thereafter, patterning those process layers using traditional photolithography and etching processes to define the gate dielectric 12 and the gate conductor 14. Thereafter, the device may be subjected to an initial ion implantation process at a relatively light concentration of dopant atoms. This initial doping process results in dopant atoms penetrating the surface 11 of the substrate 13 to a depth defined by the dashed line 19, as shown in FIG. 1. As those skilled in the art will recognize, the region formed during the initial doping process is self-aligned to the gate dielectric 12. Next, a plurality of sidewall spacers 20 are formed adjacent the gate dielectric 12 and gate conductor 14 using a variety of known techniques. For example, a layer of the appropriate material, e.g., silicon dioxide, silicon nitride, etc., may be deposited above the gate conductor 14 and the surface 11 of the substrate 13 and, thereafter, subjected to one or more anisotropic etching processes. If desired, an initial layer of silicon dioxide (not shown) may be formed above the surface 11 of the substrate 13 prior to the formation of the layer of silicon nitride. After the sidewall spacers 20 are formed, the device is then subjected to a second ion implantation process at a heavier dopant concentration to result in the final formation of the source/drain regions 16. Note that during the second doping process, the sidewall spacers 20 act as a mask to prevent the heavier dopant concentration from being implanted into the substrate 13 under the sidewall spacers 20, leaving the source/drain regions 18 generally below the sidewall spacers 20.
Those skilled in the art will recognize that the source/drain regions 16 depicted in FIG. 1 have a traditional lightly doped drain structure ("LDD") commonly encountered in modern semiconductor devices. Such LDD structures are useful for various reasons, including, but not limited to, reducing hot carrier effects in field effect transistors. The width "X" of the extension 18 of the source/drain region 16 is determined by the width of the sidewall spacer 20, as measured at the surface 11 of the substrate 13. Traditionally, sidewall spacers 20 are formed having a thickness that ranges from approximately 700-1100 .ANG.. It has been observed that, all other things being equal, transistor performance, e.g., operating speed, may be increased if the width "X" of the extension 18 of the source/drain region 16 is decreased such that it has a width as small as approximately 200 .ANG.. Of course, the performance of such transistors is a very complex activity that is governed by a variety of factors. Because the thickness of the sidewall spacers 20 approximately determines the width "X" of the extensions 18 of the source/drain regions 16, it is desirable to have a process for forming such spacers 20 that is controllable and allows formation of very thin sidewall spacers 20.
Transistors may also be subjected to a salicidation process to, among other things, decrease the resistance of the polysilicon gate conductor 14 and the source/drain regions 16. During this salicidation process, there is a potential for bridging across the sidewall spacers 20, i.e., a conductive metal silicide, e.g., titanium silicide (TiS.sub.2), may be formed across the sidewall spacers 20. This bridging can, in effect, act as a short circuit between the gate conductor 14 and the source/drain regions 16. Thus, it is desirable that sidewall spacers 20 be comprised of a material and have a profile, i.e., straighter, more vertical sidewalls, that helps to reduce or prevent this undesirable bridging by, among other things, making it easier to remove the salicide metal formed on the sidewall spacers 20. However, using existing methods and etching recipes, sidewall spacers 20 comprised of silicon nitride tend to have a more bulging, rounded profile similar to the sidewall spacers 20 depicted in FIG. 1. What is desired is a method for making very thin sidewall spacers comprised of silicon nitride that have straighter sidewalls than those currently available using existing technology.
The present invention is directed to a method and apparatus that minimizes or reduces some or all of the aforementioned problems and a method of making same.